Senior Staff Electrical Engineer - ASIC Design
Our client, a globally recognized leader in semiconductor innovation, is seeking an exceptional Senior Staff Electrical Engineer specializing in ASIC Design to join their advanced R&D team. This position, based in the vibrant tech hub of San Francisco, California, US , offers the opportunity to architect, design, and verify complex digital integrated circuits for high-performance applications. You will be at the forefront of developing next-generation semiconductor technologies.
Responsibilities: Lead the architectural definition and micro-architectural design of complex ASICs for cutting-edge products. Develop RTL (Register Transfer Level) designs using Verilog or VHDL. Perform logic synthesis, timing analysis, and physical design floor planning. Conduct comprehensive functional verification, including testbench development, simulation, and formal verification. Collaborate closely with verification, physical design, and firmware teams to ensure successful tape-out and production. Debug complex issues found during simulation, emulation, or post-silicon validation. Define and drive digital design methodologies and flows to improve efficiency and quality. Mentor junior engineers and contribute to technical knowledge sharing within the team. Stay current with the latest advancements in ASIC design, verification techniques, and semiconductor technologies. Contribute to strategic planning for future ASIC development efforts. Qualifications: Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. Minimum of 8 years of experience in digital ASIC design and verification. Proven track record of successfully designing and delivering complex ASICs from specification to production. Expertise in RTL design languages (Verilog/VHDL) and synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus). Strong experience with static timing analysis (STA) tools (e.g., Synopsys PrimeTime, Cadence Tempus). In-depth knowledge of verification methodologies (e.g., UVM, OVM) and simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). Familiarity with scripting languages (e.g., Python, Perl, Tcl) for automation. Excellent understanding of computer architecture, digital logic design, and semiconductor physics. Strong analytical, problem-solving, and debugging skills. Excellent communication and teamwork abilities. Experience with low-power design techniques and DFT (Design for Test) is a plus. This is a highly visible role with significant impact, offering the chance to work on challenging designs that power the future of technology.
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Responsibilities: Lead the architectural definition and micro-architectural design of complex ASICs for cutting-edge products. Develop RTL (Register Transfer Level) designs using Verilog or VHDL. Perform logic synthesis, timing analysis, and physical design floor planning. Conduct comprehensive functional verification, including testbench development, simulation, and formal verification. Collaborate closely with verification, physical design, and firmware teams to ensure successful tape-out and production. Debug complex issues found during simulation, emulation, or post-silicon validation. Define and drive digital design methodologies and flows to improve efficiency and quality. Mentor junior engineers and contribute to technical knowledge sharing within the team. Stay current with the latest advancements in ASIC design, verification techniques, and semiconductor technologies. Contribute to strategic planning for future ASIC development efforts. Qualifications: Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. Minimum of 8 years of experience in digital ASIC design and verification. Proven track record of successfully designing and delivering complex ASICs from specification to production. Expertise in RTL design languages (Verilog/VHDL) and synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus). Strong experience with static timing analysis (STA) tools (e.g., Synopsys PrimeTime, Cadence Tempus). In-depth knowledge of verification methodologies (e.g., UVM, OVM) and simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). Familiarity with scripting languages (e.g., Python, Perl, Tcl) for automation. Excellent understanding of computer architecture, digital logic design, and semiconductor physics. Strong analytical, problem-solving, and debugging skills. Excellent communication and teamwork abilities. Experience with low-power design techniques and DFT (Design for Test) is a plus. This is a highly visible role with significant impact, offering the chance to work on challenging designs that power the future of technology.
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