[Remote] Principal ASIC Physical Design Engineer

Note: The job is a remote job and is open to candidates in USA. K2 Space Corporation is building the largest and highest-power satellites ever flown, aiming to unlock unprecedented performance levels across various orbits. They are seeking a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite systems, overseeing the full physical design flow and collaborating with various teams to ensure the success of their innovative projects.ResponsibilitiesOwn the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-offDevelop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA)Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iterationDrive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified toolsPartner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integrationManage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standardsWork with EDA vendors to debug and optimize tool flows, and evaluate new methodologiesSupport chip bring-up and debug through close collaboration with post-silicon and test teamsSupport your product through production and spaceflightSkillsBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field10+ years of experience in ASIC physical design for high-performance SoCsProven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens)Strong hands-on experience with timing closure, IR drop analysis, and ECO implementationDeep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCsExperience with advanced FinFET process nodesPrior experience managing or coordinating offshore/outsourced PD teams or vendorsFamiliarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF)Excellent communication, leadership, and cross-functional collaboration skillsAct as technical leader and subject-matter expert helping to teach, grow, and mentor others in the teamExposure to radiation-hardened or space-qualified ASICsExperience with chip-package co-design or advanced packaging (2.5D/3D)Familiarity with physical design service vendor management or offshore collaborationExperience driving tapeouts through TSMCExperience with Gate-All-Around technologiesExperience working in cross-functional, geographically distributed teamsBenefitsEquity in the companyComprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perksCompany OverviewMaking previously impossible missions possible It was founded in 2022, and is headquartered in Torrance, California, USA, with a workforce of 51-200 employees. Its website is https://www.k2space.com.