**Job Title:**
Chip Level Library & Design Optimization Engineer - Join Our Innovative Team in Apple Valley, CA ($23/Hour)
**Job Description:**
We're seeking a highly skilled and motivated Chip Level Library & Design Optimization Engineer to join our cutting-edge team in Apple Valley, CA. As a key member of our Computerized Plan IP group, you'll play a vital role in transforming innovative ideas into reality. Your expertise will drive success in designing and optimizing custom ASICs, working closely with our team to bring clients unparalleled experiences.
This is a full-time, remote opportunity with a competitive salary of $23/hour. If you're passionate about silicon design, process innovation, and collaboration, we encourage you to apply.
**Key Responsibilities:**
* Demonstrate a deep understanding of advanced CMOS device behavior, including material science and analysis, and their impact on SoC design PPA metrics.
* Develop and apply yield (product or technology learning vehicle) knowledge, including defect Pareto improvement and Failure Investigation philosophies, Benchmarking practices.
* Utilize strong data analysis and statistical examination skills, with proficiency in a wide range of data analysis tools for both device and yield investigation.
* Perform fundamental circuit analysis, extraction, and spice recreation for PPA benchmarking applications.
* Foster excellent communication and collaboration skills to drive success within and outside the team, working closely with leadership, management, and external partners.
**Ideal Candidate:**
* Bachelor's degree in Electrical Engineering, Computer Science, or related field.
* At least 3 years of relevant industry experience.
* Strong understanding of cutting-edge CMOS device behavior, yield analysis, and data analysis tools.
* Excellent communication, collaboration, and problem-solving skills.
**Join Our Team:**
We're a dynamic and innovative team dedicated to shaping the future of technology. As a Chip Level Library & Design Optimization Engineer, you'll have the opportunity to work on cutting-edge projects, collaborate with a talented team, and contribute to the development of custom IP solutions that drive innovation.
Apply Now
Apply Now
**Job Description:**
We're seeking a highly skilled and motivated Chip Level Library & Design Optimization Engineer to join our cutting-edge team in Apple Valley, CA. As a key member of our Computerized Plan IP group, you'll play a vital role in transforming innovative ideas into reality. Your expertise will drive success in designing and optimizing custom ASICs, working closely with our team to bring clients unparalleled experiences.
This is a full-time, remote opportunity with a competitive salary of $23/hour. If you're passionate about silicon design, process innovation, and collaboration, we encourage you to apply.
**Key Responsibilities:**
* Demonstrate a deep understanding of advanced CMOS device behavior, including material science and analysis, and their impact on SoC design PPA metrics.
* Develop and apply yield (product or technology learning vehicle) knowledge, including defect Pareto improvement and Failure Investigation philosophies, Benchmarking practices.
* Utilize strong data analysis and statistical examination skills, with proficiency in a wide range of data analysis tools for both device and yield investigation.
* Perform fundamental circuit analysis, extraction, and spice recreation for PPA benchmarking applications.
* Foster excellent communication and collaboration skills to drive success within and outside the team, working closely with leadership, management, and external partners.
**Ideal Candidate:**
* Bachelor's degree in Electrical Engineering, Computer Science, or related field.
* At least 3 years of relevant industry experience.
* Strong understanding of cutting-edge CMOS device behavior, yield analysis, and data analysis tools.
* Excellent communication, collaboration, and problem-solving skills.
**Join Our Team:**
We're a dynamic and innovative team dedicated to shaping the future of technology. As a Chip Level Library & Design Optimization Engineer, you'll have the opportunity to work on cutting-edge projects, collaborate with a talented team, and contribute to the development of custom IP solutions that drive innovation.
Apply Now
Apply Now